The escalating requirements for high density and performance associated with ultra-large scale integration semiconductor devices necessitate design features of 0.18 micron and under, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput. The reduction of design features to 0.18 micron and under challenges the limitations of conventional interconnection technology, such as the electrical isolation properties of interlevel dielectric (ILD) materials.
A problem encountered in highly miniaturized semiconductor devices employing multiple levels and reduced interwiring spacings in both the horizontal and vertical dimensions is related to the resistance-capacitance (RC) time constant of the system. Although semiconductor devices are presently being scaled in the horizontal dimension, they are not generally scaled in the vertical dimension, since scaling in both dimensions would lead to a higher current density that could exceed reliability limits. Horizontal scaling, however, requires conductive lines having a high aspect ratio, i.e., ratios of conductor height to conductor width greater than one, e.g., three or four, along with reduced interwiring spacings. As a consequence, capacitive coupling between conductive lines becomes a significant limitation on circuit speed. If intrametal capacitance is high, electrical inefficiencies and inaccuracies increase. It has been recognized that a reduction in capacitance within multi-level system will reduce the RC time constant between the conductive lines.
The drive towards increased miniaturization and the resultant increase in the RC time constant have served as an impetus for the development of newer, low dielectric constant ("low k") materials as substitutes for conventional higher dielectric constant silicon oxide-based ILD materials. However, such dielectric materials must be able to serve a number of different purposes requiring diverse characteristics and attributes. For example, the ILD material must: prevent unwanted shorting of neighboring conductors or conducting levels by acting as a rigid, insulating spacer; prevent corrosion and/or oxidation of metal conductors, by acting as a barrier to moisture and mobile ions; fill deep, narrow gaps between closely spaced conductors; and undergo planarization of uneven surface topography so that a relatively flat level of conductors can be reliably deposited thereon. In addition, ILD films or layers must be formed at relatively low temperatures (i.e. no greater than about 450.degree. C.) to avoid damage to or destruction of underlying conductors. Another, and important consideration in regard to RC time constant effects, is that such dielectric films used as ILD materials must have a low dielectric constant, as compared to the value of 4.1 to 3.9 for a conventionally employed silicon dioxide (SiO.sub.2) layer, in order to reduce the RC time constant, lower power consumption, reduce crosstalk, and reduce signal delay in closely spaced conductors.
Silicon oxide has found the widest application as ILD layers in multilevel interconnect technology partly because of the familiarity and varied methods for depositing silicon oxide layers pervasive in semiconductor manufacturing processes. Silicon oxide as ILD layers can be deposited by any number of processes, including chemical vapor deposition (CVD), plasma enhanced CVD and liquid spin-on glass forming techniques, tailored to achieving high-quality ILDs characterized by good electrical and physical properties. Accordingly, it would be highly advantageous to utilize current techniques of forming silicon oxide as ILDs with an improved lower dielectric constant to further reduce device features.
It has been observed in the art of virtrified fission products that radiation can cause decomposition of the lattice structure of a silicate glass resulting in the formation of bubbles within the glass. DeNatale et al. "Importance of Ionization Damage to Nuclear Waste Storage in Glass", Ceramic Bulletin (1987) 66, 1393-1396; Howitt et al. "Mechanism for the Radiolytically Induced Decomposition of Soda-silicate Glasses", J. Am. Ceram. Soc. (1991) 74, 1145-1147. Efforts in the art of virtrified fission products, however, attempt to improve or ameliorate the decomposition of glasses exposed to radiation from waste nuclear material primarily by reducing the bubble or void formation in the glass thereby improving long-term storage capability of the virtrified waste products. See, e.g. De et al. "Development of Glass Ceramics for the Incorporation of Fission Products", Ceramic Bulletin (1976) 55, 500-503.However, it is believed that a process for achieving beneficial electrical properties of irradiated glasses has not been recognized or undertaken within the semiconductor manufacturing art.
Baglin et al., in U.S. Pat. No. 4,001,049, disclose a method for improving the dielectric breakdown strength of an amorphous silicon dioxide (SiO.sub.2) film by ion implantation in conjunction with an annealing treatment of the film. The SiO.sub.2 films are reported to be highly densified, lacking micropores and particularly applicable to thin gate oxide structures. ILD layers, however, differ significantly in desired properties and structures from that of oxide films used in field effect transistors. For example, ILD layers can not be exposed to high temperatures without damage to or destruction of underlying conductors. Moreover, the dielectric strength of the ILD is less important since the ILD primarily functions to electrically isolate conductive layers and not under a high capacitive environment.
Thus, there exists a need for utilizing current techniques of depositing ILD layers but improving the dielectric constant thereof, particularly as employed in the manufacture of ultra large scale integration semiconductor devices having multiple levels.